Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs

A theoretical analysis of a recently proposed phase-noise cancellation technique that relaxes the fundamental tradeoff between phase noise and bandwidth in (delta)(sigma) fractional-N phased-locked loops (PLLs) is presented. The limits imposed by circuit errors and PLL dynamics on the phase noise and loop bandwidth that can be achieved by PLLs incorporating the technique are quantified. Design guidelines are derived that enable customization of the technique in terms of PLL target specifications.