Abstract :
In this experiment, tantalum pentoxide (Ta2O5) was used in a metal/oxide/high-k Ta2O5/oxide/silicon (MOHOS) novel nanocrystal memory as a trapping layer. Post-annealing treatment, which can passivate defects and improve the material quality of the high-k dielectric, was applied to optimize device performance for a better memory window and faster P/E (program/erase) cycle. Material and electrical characterization techniques including X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and electrical measurements were performed to analyze the device under different annealing conditions. The Ta2O5 charge trapping layer memory annealed at 900 °C had a higher window of 3.3 V in the current–voltage (C–V) hysteresis loop, and a higher charge retention capability than the samples prepared under various annealing conditions. These higher levels were due to the higher probability of deep-level charge trapping and lower leakage current.
Keywords :
Deep-level , Charge trapping , Ta2O5 , High-k material , Post annealing