Lateral current confinement in selectively grown resonant tunneling transistor with an embedded gate

We report on fabrication and measurements of a selectively grown vertical resonant tunneling transistor with lateral current constriction. A GaInP/GaAs/GaInP, 3/9/3 nm, double barrier structure is epitaxially grown over a grating of tungsten (W) wires, where the Schottky depletion around the embedded wires creates a semi-insulating layer. The vertical current in the device passes the semi-insulating region through a designed opening (View the MathML source) in the grating, which, taking the depletion region into account, gives a transistor with an electrical area of well below View the MathML source. Current–voltage (I–V) measurements at 4 K show a multitude of current peaks that respond strongly to the gate voltage applied to the metal grating. From the gate response and the small lateral area, we believe that these peaks arise from lateral confinement effects.