Silicon nano-transistors for logic applications

Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the “nano-transistor” regime. This paper discusses performance characteristics of a MOSFET device with View the MathML source physical gate length. In addition, aspects of a non-planar CMOS technology that bridges the gap between traditional CMOS and the nano-technology era will be presented. It is likely that this non-planar device will form the basic device architecture for future generations of nano-technology.