A compensation method for time delay of full-digital synchronous frame current regulator of PWM AC drives

The voltage output is inevitably delayed in a full-digital implementation of a current regulator due to an arithmetic calculation and the pulsewidth modulation. In the case of the synchronous frame current regulator, the time delay is accompanied by a frame rotation. In some applications where the ratio of the sampling frequency to the output frequency is insufficient, such as a high-power drive or a super-high-speed drive, the effect of the frame rotation during the delay time causes a phase and magnitude error in the voltage output. The error degrades the dynamic performance and can cause instability in the current regulator at high speed. It is also intuitively known that advancing the phase of the voltage output can mitigate this instability. In this paper, the errors in the voltage output and the instability problems have been studied analytically and a compensation method for the error is proposed. Using a computer simulation and complex root locus analysis, a comparative study with conventional methods has been carried out and the utility of the proposed method has been verified experimentally.