Analysis, implementation and application of an ordered statistics decoder for the seRS(16,14) code

The authors present an analysis and the FPGA implementation of an ordered statistics decoder for the singly extended ReedSolomon code seRS(16,14). The goal of the design is to maintain good performance while reducing computational complexity and area with respect to the maximum-likelihood decoder of the same code or a Viterbi decoder of a high-rate punctured convolutional code of comparable performance. The authors also analyse a multilevel coded modulation system based on the partition chain E/sub 8//RE/sub 8//2E/sub 8/, that makes use of a rate-1/2 16-ary convolutional code at the first level and of the seRS(16,14) code at the second level. This scheme is well suited to STM1 data transmission (155.52 Mbit/s) with 28 MHz channel spacing and 256 QAM modulation.