Title of article :
Drain voltage induced barrier increasing of quantum-wire transistors
Author/Authors :
A.، Forchel, نويسنده , , S.، Reitzenstein, نويسنده , , L.، Worschech, نويسنده , , D.، Hartmann, نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2004
Pages :
-74
From page :
75
To page :
0
Abstract :
In-plane quantum-wire transistors based on a modulation-doped GaAs/AlGaAs heterostructure are studied in the threshold regime. It is found that the threshold voltage V/sub T/ of a quantum wire transistor depends on the applied bias voltage in a parabolic way. In particular, V/sub T/ increases in the strong nonlinear transport regime with increasing bias voltage, which is in contrast to the drain voltage induced barrier lowering observed for submicron transistors. The increase of V/sub T/ by a barrier increase along the channel with increasing bias voltage due to a self-depletion is explained.
Keywords :
Hydrograph
Journal title :
IEE Electronics Letters
Serial Year :
2004
Journal title :
IEE Electronics Letters
Record number :
106999
Link To Document :
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