Title of article
Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports
Author/Authors
T.، Hirakawa, نويسنده , , H.J.، Mattausch, نويسنده , , T.، Koide, نويسنده , , T.، Hironaka, نويسنده , , K.، Johguchi, نويسنده , , Z.، Zhu, نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2004
Pages
-15
From page
16
To page
0
Abstract
A proposal to improve the low access bandwidth of conventional one-port caches by utilising a multi-bank structure with distributed crossbar to increase port number at small additional area cost is presented. This enables combination of data and instruction caches into a single multi-port cache as well as different wordlength for each port. Through dynamically scheduling the storage space used for data and instructions, 25% smaller storage capacity is sufficient for a given maximum cache-miss probability.
Keywords
Hydrograph
Journal title
IEE Electronics Letters
Serial Year
2004
Journal title
IEE Electronics Letters
Record number
107054
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