Rail-to-rail low-power high-slew-rate CMOS analogue buffer

A low-power rail-to-rail CMOS analogue buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, resulting in suitability for applications with large capacitive loads. Simulated results are provided.