Author/Authors :
H.S.، Cho, نويسنده , , Y.J.، Choi, نويسنده , , K.-Y.، Chang, نويسنده , , D.W.، Hong, نويسنده ,
Abstract :
A trade-off between performance and area is important to design an efficient hardware structure for arithmetic operations in GF(2/sup m/). Proposed is a hybrid multiplier for GF(2/sup m/) with an irreducible trinomial, which can be constructed in variable structures depending on such a performance area trade-off.
