An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition Original Research Article

Computer-Generated Hologram (CGH) is well known to take an enormous computational time. We propose an efficient computational method for CGH suitable for hardware devices, which are fixed-point DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit). To be concrete, this method can compute a phase on a hologram by addition. When we operated this method on a personal computer, we could maximally compute CGH about 24 times faster than a traditional method. And also, when we adopted this method to FPGA chip, we could implement circuits about 5 times more than a traditional method.