Automatic implementation of affine iterative algorithms: Design flow and communication synthesis Original Research Article

This work addresses the automatic generation of a parallel architecture, described by the skeleton of a VHDL program at the Register Transfer Level, starting from some high level expression specified by the LIGHTC language, a subset of the ANSI C. The synthesis methodology is related to the affine iterative algorithms, which arise in many scientific and technological applications and can be described by the System of Affine Recurrence Equations model (SARE). After reviewing basic theory on SARE and their synthesis, we present a new methodology to synthesize communications: the proposed communication synthesis methodology, based on a propagation technique which uses the concept of Integral Hilbert Vector basis, allows the generation of inexpensive (in terms of time and silicon area) communication patterns. The communication synthesis methodology is part of a global design flow: the main steps of the design flow are shortly reviewed and the whole design methodology is explained by a simple test case, the matrix–matrix product.