Title of article
Mapping application performance to HPC architecture Original Research Article
Author/Authors
A. Gray، نويسنده , , I. Bethune، نويسنده , , R. Kenway، نويسنده , , L. Smith، نويسنده , , Thomas M. Guest MD، نويسنده , , C. Kitchen، نويسنده , , P. Calleja، نويسنده , , A. Korzynski، نويسنده , , G. L. S. Rankin، نويسنده , , M. Ashworth، نويسنده , , A. Porter، نويسنده , , I. Todorov، نويسنده , , Kim M. Plummer، نويسنده , , E. Jones، نويسنده , , L. Steenman-Clark، نويسنده , , Philip W. Kuchel, Gregory B. Ralston، نويسنده , , C. Laughton، نويسنده ,
Issue Information
ماهنامه با شماره پیاپی سال 2012
Pages
10
From page
520
To page
529
Abstract
A suite of application benchmarks, designed to be broadly representative of UK HPC usage, has been developed to stress a broad range of architectural features of large scale parallel HPC resources. A generic methodology to investigate application performance and scaling characteristics has been defined, resulting in a detailed understanding of the performance of these applications. This methodology is transferable to other applications and systems: it is of practical value to developers and users who are aiming for optimal utilisation of HPC resources. An understanding of the performance characteristics of a range of large-scale HPC resources has been obtained using low-level synthetic benchmarks. A relatively simple, qualitative mechanism to assess and predict application performance on current and future architectures using synthetic benchmark results together with application performance analysis results is explored.
Keywords
Performance analysis , Benchmarking , High performance computing
Journal title
Computer Physics Communications
Serial Year
2012
Journal title
Computer Physics Communications
Record number
1138512
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