Power cycling thermal fatigue of Sn–Pb solder joints on a chip scale package

Tin-Lead (Sn-37wt%Pb) eutectic solder joints on a chip scale package (CSP) attached to a printed circuit board have been tested under power cycling from 0 to 100 °C each cycle. Fatigue failure by near interfacial crack growth was discovered to progress from the outside edge of the joints towards the center of the package, for all joints. Creep/fatigue and shear overload microscopic failure modes were found on the solder joint fracture surfaces. The eutectic microstructure of the joints was found to coarsen as the thermal cycling took place, changing the inherent material properties besides accumulating damage. Voids and secondary cracks were shown to have an insignificant effect on the rate and direction of fatigue crack growth compared to the location of the joint on the package, which determines the stress on the joint. The fracture morphology due to fatigue crack growth was nearly identical close to and far from the crack initiation site, revealing similar damage mechanisms during all stages of life. Nonlinear finite element analyses were carried out to estimate the state of stress and inelastic strain in the solder joints under the imposed thermal cycling conditions. Transient heat transfer analysis followed by a structural analysis including plasticity and creep effects was performed using three-dimensional models. The maximum inelastic strains, obtained using the finite element simulation were compared against the crack propagation area at equivalent cycle numbers for several solder joints along the diagonal cross-section of the package. The crack propagation area and the inelastic strain correlated well irrespective of the presence of solder defects, such as voids. A damage-based model is introduced to analyze crack trajectory in the solder joints. The proposed model enables a computationally efficient algorithm for fatigue lifetime and crack front progression estimation in solder joints.