Architecture for fractal image compression

The algorithms for fractal image compression impose a heavy demand on the processorʹs arithmetic unit and the memory interface, failing to utilize the full capabilities of a generalpurpose processor. The repetitive nature of the algorithm indicates that parallelization would reduce the time complexity of the otherwise expensive encoding scheme. In this paper, the design of an ASIC for FIC is proposed. This exploits the fact that the algorithm requires only integer arithmetic with repetitive use of the same set of data. Controlled parallelism is introduced by way of multiple functional units. These result in an encoding time 75 times faster than the high-level software implementation and 22 times faster than the assembly level implementation on a DSP processor.