ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs

Technology mapping for Multiplexor (MUX) based field programmable gate arrays (FPGAs) has widely been considered. Here, a new algorithm is proposed that applies techniques from logic synthesis during technology mapping, i.e., the target technology is considered in the minimization process. Binary decision diagrams (BDDs) are used as an underlying data structure combining both structural and functional properties. The algorithm uses local donʹt cares obtained by a greedy algorithm. To evaluate a netlist, a fast technology mapper is used. Since most of the changes to a netlist are local, re-mapping can also be done locally, allowing a fast but reliable evaluation after each modification. Both area and delay minimization are addressed in this paper. We compare the approach to several previously published algorithms. In most cases these results can be further improved. Compared to SIS, an improvement of 23% for area and 18% for delay can be observed on average.