Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism

As instruction window size increases, it becomes difficult to maintain processor cycle time. Pipelining the window is not a solution, since it is said that it affects processor performance seriously. However, the pipelining has not been evaluated quantitatively. On the other hand, recent interests on data speculation demand to increase the window size to realize instruction reissue mechanism which deals with misspeculations. For reducing the window size with maintaining the instruction reissue capability, we propose to decouple the reissue mechanism from the scheduling mechanism. Based on simulations, we have evaluated the pipelining and the decoupling of the instruction window.