Author/Authors :
Onuki، Jin نويسنده , , Chonan، Yasunori نويسنده , , Komiyama، Takao نويسنده , , Nagano، Takahiro نويسنده , , Akahoshi، Haruo نويسنده , , Itabashi، Takeyuki نويسنده , , Saito، Tatuyuki نويسنده , , Khoo، Khyoupin نويسنده ,
Abstract :
Copper electroplating has been used for making interconnections in large-scale integration (LSI). Sub-100-nm-wide, deep trenches with aspect-ratios over 6 were fully filled by optimizing DC and pulse electroplating processes. Grain sizes of Cu of sub-100-nm wide trenches after electroplating were 70 nm for DC electroplating and 58 nm for pulse electroplating. The Cu grain sizes of Cu interconnects by DC plating after electroplating increased with the annealing temperature.
Keywords :
Semiconductor , annealing , electroplating , Copper
