Wire density in CAE analysis of high pin-count IC packages: Simulation and verification

Wire sweep has been recognized as one of the major defects in the encapsulation of microelectronic chips by the transfer molding process. As thinner and denser IC packages emerge, wire-sweep analysis becomes more challenging and troublesome. This paper studies the reactive flow in IC encapsulation by the CAE molding simulation and the wire-sweep phenomena. In fact, it presents a new methodology used to consider the effect of wire density (number of wire) by controlling the shape factor to simulate the flow resistance. The results show a better solution for melt-front advancement and wire-sweep prediction. Finally, one study case for high pin-count packages (BGA) is used to verify the research.