High-G drop impact response and failure analysis of a chip packaged printed circuit board

This paper is concerned with constructing a high-G drop impact test condition for investigating the impact-induced failure phenomenon of the solder ball array located in the chip packaged printed circuit board. An impact environment satisfying the JEDEC B service conditions, requiring a 0.5 ms half-sine impact pulse duration with a peak acceleration at 1500 G, were constructed using an instrumented drop tower tester. Fifteen wafer-level CSP chips were installed on a standard printed circuit board (PCB) with a dimension of 132×77×1 mm3. A number of these chip packaged PCB bonded with four different compositions of solder joints with or without lead using the surface-mounted technology (SMT) were studied. During the drop impact tests, the chip packaged PCB circuit was monitored using the multi-event detector system (ETAC) to examine whether circuit fails or not. In addition, the drop impact dynamic response of the PCB and the acceleration at the prescribed location of the drop table were recorded and analyzed. Transient stress responses in the solder joints were provided using the LS-DYNA explicit code. Numerically predicted failure locations of the solder joints are close to those observed from actual drop impact experiments.