ESD protection design challenges for a high pin-count alpha microprocessor in a 0.13 μm CMOS SOI technology ☆

We illustrate the complexity of designing ESD protection for a 64-bit microprocessor employing 140 million transistors. This IC contains 901 I/O signals, most operating at >l Gbit/s/pin, and 10 power supplies split into 27 domains. An extensive set of CAD tools used to expedite ESD-related chip assembly and to analyze finished layout is described.