Thermal resistance degradation of surface mounted power devices during thermal cycling

Backside scanning acoustic tomography (SCAT) images have been correlated to alloy morphology (cross-section) and composition data (stoichiometry) to model the (theta)jc degradation for surface mounted device packaged power ICs as a function of the temperature cycling range. We find that an appropriate setting of the die attach process can suppress needle-shaped Cu3Sn in favor of roughly spheroid Cu6Sn5. We derived, from the degradation of the (theta)jc during thermal cycling stress tests with different temperature swings, an acceleration factor with the use of the Coffin-Manson law. The fit parameter q in this formula is 9.3 for the new improved setting of the die attach process when the high SO power (HSOP) package is used. The moisture sensitivity level has no significant influence. Finally, a maximum (theta)jc degradation of 0.33 K/W based on the normal distribution approach results in a minimum lifetime of 12 years. When a customer requires a maximum (theta)jc of 2.0 K/W at the end of life, 50 years can be guaranteed.