Title of article
Extended SPICE-like model accounting for layout effects on snapback phenomenon during ESD events.
Author/Authors
Mortini، P. نويسنده , , Salome، P. نويسنده , , Richier، C. نويسنده , , Essaifi، S. نويسنده , , Zaza، I. نويسنده , , Juge، A. نويسنده , , LEROUX، C. نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 1999
Pages
-832
From page
833
To page
0
Abstract
An extended SPICE-like model for snapback phenomenon including the impact of gate length and substrate on the holding voltage is presented. Substrate conduction is analytically solved thanks to a transmission line model. A fast extraction methodology is also described. This model is in good agreement with the measurements performed on deeply submicron CMOS technologies. © 1999 Elsevier Science Ltd. All rights reserved.
Keywords
Resistance measurements , Aluminum alloys , Microstructural analysis , Electromigration
Journal title
MICROELECTRONICS RELIABILITY
Serial Year
1999
Journal title
MICROELECTRONICS RELIABILITY
Record number
13015
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