ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration

We demonstrate that NMOS transistors stacked in a cascode configuration provide robust ESD protection for mixed voltage I/O in both silicided and silicide-blocked technologies. Circuits for gate voltage modulation were added to ensure uniform finger triggering of the fully silicided device. Layout and circuit rules were developed to avoid parasitic breakdown paths. © 1999 Elsevier Science Ltd. All rights reserved.