Author/Authors :
Motallebzadeh، Vahid نويسنده Department of Electrical Engineering, Sadjad Institute of higher Education, Mashhad, Iran , , Alamdar، Mohammad Reza نويسنده Department of Electrical Engineering, Sadjad Institute of higher Education, Mashhad, Iran , , Izadpanah Tous، Saber نويسنده Department of Electrical Engineering, Sadjad Institute of higher Education, Mashhad , , Golmakani، Abbas نويسنده 3- Department of Electrical Engineering, Sadjad Institute for Higher Education, Mashhad ,
Abstract :
In this paper a novel 1-bit full adder using hybrid-CMOS logic style is proposed.Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adder with desired performance.The new proposed full adder is based on differential cascade voltage switch logic (DCVSL) XOR-XNOR gate which generate full-swing outputs.The complementary pass-transistor logic (CPL) is used to have minimum propagation delay and stability against noise in the Sum signal. Also the transmission-gate logic (TG) is used to have high speed and full-swingin Cout signal. The circuit that consists of 16 transistors is simulated with HSPICE in 0.18 ?m CMOS process by varying supply voltages from 1V to 1.8 V with 0.2V steps.The simulation results show that the proposed circuit has less power consumption and is faster in comparison to the other circuits.
