1.5–2.5 nm RTP gate oxides: process feasibility, properties and limitations

To support the international roadmapsʹ requirements, semiconductor manufacturers must develop new processing technologies, both to shrink the dimensions and to improve the performances of devices. As a consequence, gate oxidation must advance to the 1.5–2.5 nm range over the coming years, to support the sub-0.18 μm technologies. We present here an overview of the more critical concern regarding this gate oxide downscaling. The limitations of rapid thermal processed (RTP) gate dielectric for oxide thickness <2 nm are discussed in terms of process feasibility, oxide thickness determination and maximum gate leakage current. As a result, we show that oxides as thin as 1.2 nm can be processed with control of the film uniformity (range within 0.06 nm). However, we also demonstrate that the exponential increase of the gate leakage current for oxides <2 nm does not allow integrating such thin dielectric layers in present metal oxide semiconductor (MOS) devices (oxide thickness limit around 2.3 nm).