Digital-lithographic processing for thin-film transistor array fabrication

Digital lithographic patterning was used to fabricate thin-film transistor devices (TFTs). In one case, hydrogenated amorphous silicon (a-Si:H) TFTs were fabricated using a jet-printed masking method to pattern device features in place of photolithography. Device characteristics were comparable to conventional a-Si:H TFTs with a typical threshold voltage (VT) of 0.3 V, a carrier mobility (μ) of 0.7 cm2/V s, and an on/off ratio of 108. In a second case, solution processable polymeric semiconductors were used to fabricate all print patterned TFTs. These devices had an average VT=−3 V, μ=0.1 cm2/V s, and an on/off ratio of 106. a-Si:H TFT arrays having 64 × 64 pixels with 300 μm pitch were fabricated using digital lithography.