Amorphous silicon junction field-effect transistor with low pinch-off voltage for analog applications

In this paper we report on the modeling and formation of a junction field effect transistor for linear circuits based on amorphous silicon materials. Although the device behaves basically as the corresponding crystalline device, modeling of the depletion process of the channel, controlling the device operation, has to be performed in order to take into account the effect of the high defect density in doped amorphous silicon. To this aim, we used a one-dimensional finite-difference device simulator, which provides design specifications for a transistor which works properly with a few volts for both drain/source voltage and gate/source voltage. Based on simulation results a device with W/L=400 μm/40 μm was fabricated. The measured output characteristics show pinch-off voltages around −3.6 V and transconductance values of the order of 10−7 A/V. These performances are better than the ones obtained from state of the art thin-film transistor and make the device suitable for application as amplifier.