Underlying reverse current mechanisms in a-Si:H p+–i–n+ solar cell and compact SPICE modeling

The defect states in bulk of i-layer and at p+/i interface have been studied by using dark reverse current–voltage (J–V) measurements. The dark reverse current as a function of voltage has been analyzed on the basis of thermal generation of the carriers from mid-gap states in i-layer. Based on its behavior the thermal generation mechanism has been divided into two types. Thermal generation at lower bias (<5 V) shows V1/2 behavior, whereas at higher bias follows an exponential dependence of voltage (>5 V). This was explained using a thermal generation zone at lower bias, which is a source of reverse currents, and its evolution towards p+/i interface with increasing voltage. The analytical result has shown that at lower reverse bias (V < 5 V) the defect states in the bulk of i-layer and at higher bias (V ∼ 25 V) the defect states at p+/i interface are contributing to the reverse currents. Reverse bias annealing (RBA) treatment which has been performed on these cells shows that a reduction of defect states more in the i-region near to the p+-layer and at p+/i interface as compared to the deep regions in bulk of i-layer. The calculated defect state density (DOS) is varying from its intrinsic value of 2.4 × 1017 cm−3 in the bulk of the i-layer up to 2.1 × 1019 cm−3 near and at p+/i interface. These values decrease to 7.1 × 1016 cm−3 and 2.7 × 1017 cm−3, respectively, in the samples annealed under reverse bias at 2 V. The bias dependent leakage current behavior has been modeled and implemented in simulation program with integrated circuit emphasis (SPICE) using simple circuit elements based on voltage controlled current sources (VCCS). Simulated and measured reverse leakage current characteristics are in reasonable agreement.