Shared cache architectures for decision support systems

In this paper we evaluate two shared-cache architectures for small-scale multiprocessors. We vary shared cache sizes from 8MB to 1GB, under various block sizes, cache organizations and sizes, and strategies for IO transactions. We use 12 bus trace samples obtained during the execution of a 100GB TPC-H on an eight-way multiprocessor. l with the cold-start misses at the beginning of each sample, we identify the sure misses which are known to be misses in the full trace. The difference between the total number of misses and the number of sure misses is the zone of uncertainty, which may be hits or misses in the full trace. It turns out that the zone of uncertainty is small enough in most cases that useful conclusions can be drawn. nclusions are that a single-cluster configuration with a shared cache—even a very small one—can be very effective for TPC-H. We also show that the coherence traffic between shared caches in a multiple cluster system is very high in the context of TPC-H.