Hardware programmable VLSI emergency shutdown system

As the required intelligence of systems increases so does their complexity, to the extent that their design is becoming less and less manageable. The issue of complexity explosion and its management during the product design phase is examined through the design and design implementation of a VLSI Emergency Shutdown System (ESD) chip. Highly structured Algorithmic State Machine (ASM) design techniques are used to achieve a hardware programmable and flexible implementation of the product specification. The chip is capable to monitor up to four but upward extendable process variables and activate a shutdown operation if any one of the variables falls outside predetermined limits. It is supported by a single operator interface panel that controls and observes the operation of all channels. aper, in two parts, describes the results of a research effort to design a general purpose VLSI ESD system which aims to achieve a level of reliability and testability exceeding current implementations.