Design and Analysis of Three New SRAM Cells

Three new SRAM cells are proposed in this paper. Increasing area overhead is the major concern in SRAM design. One of the new structures is included four transistors instead of six transistors as it is used in conventional 6T-SRAM cell for very high density embedded SRAM applications. The structure of proposed SRAM employs one word-line and one bit-line during Read/Write operation. The new SRAM cell has smaller size, leakage current and power dissipation in contrast of a conventional six transistor SRAMs. A proposed 4T-SRAM cell has been simulated for 256 cells per bit-line and 128 columns cell for supply voltage of 1.2V. Furthermore, two other new structures are included 10 and 11 transistors. These new structures have been separate read and write process by changing in the structure of conventional 6T SRAM to achieve high Static Noise Margin (SNM). Using 10T and 11T SRAM cells lead to apply 512 cells per bit-line by reducing leakage current technique, while the cell is unavailable. 128 columns cell array has been built to measure the operation of SRAM cell. To have low power dissipation, the supply voltage for 10T and 11T are chosen 0.32V and 0.27V, respectively. Proposed SRAM uses one read bit-line during read operation. Simulation results have been confirmed by HSPICE in 0.13um process.