Electronic and dielectric properties of a suboxide interlayer at the silicon–oxide interface in MOS devices

We study the electronic structure and the dielectric permittivity of ultrathin oxide layers on Si(1 0 0) substrates. By considering two different Si(1 0 0)–SiO2 interface models, we first show that the electronic structure in the interfacial oxide differs from the corresponding bulk counterpart due to silicon-induced gap states. Then, we calculate the permittivity of the first few angstroms of the oxide within a density-functional approach. For sub-nanometric oxides, we find that the oxide permittivity increases when the thickness is reduced, and we interpret this result in terms of the series capacitance of the pure oxide and of a substoichiometric interface layer. Based on a description of the dielectric screening in terms of polarizable units, we show that the enhanced permittivity of the suboxide region originates from the larger polarizability of Si atoms in partial oxidation states. Finally, we discuss the implications of our findings for interfaces between silicon and high-κ gate oxides.