Exploring the VLIW Architecture Space for Network Applications

The increasing diversity in packet-processing applications together with the rapid increase in channel bandwidth has brought about greater complexity in communication protocols. Also influenced by these factors is the computational load for packet-processing engines, demanding high performance microprocessor designs as an indispensable solution. This paper reports on extensive simulation experiments carried out for exploring the performance of instruction-level parallel Very Long Instruction Word (VLIW) processors executing packet-processing applications. On the grounds of the experimental results, a design space exploration has been used to derive an efficient application-specific VLIW processor architecture based on the VEX instruction set architecture. The VEX simulator toolset has been used for design space exploration, and a number of networking applications have been chosen to serve in guiding the architectural exploration. The optimization measures achieve up to 60% improvement in performance for the most representative packet-processing applications.