Placement Algorithms and Logic on Logic (LOL) 3D Integration

In the present study, three algorithms for placement of standard 3D cells have been analyzed. These algorithms are 3D placement using 2D placement devices, real 3D analytic placement using mPL, and 3D placement simultaneously using 2D and mPL placements. These algorithms are used to place three case studies in a real face-to-face 3D process. These three case studies include: two-point FFT butterfly processing element known as PE, advanced embedded series or AES, and wireless decoding with multiple input and multiple output (MIMO). Afterwards, displacements are compared with 2D placements regarding performance and power consumption. Then, using this technology, i.e. face-to-face 3D integration with micro bump along with three placement algorithms, timer speeds of AES and PE modules are respectively increased as 3.15% and 6.22% while their power consumption are reduced to 6.2% and 9.12%, respectively.