Author/Authors :
Min، نويسنده , , Kyeong-Sik and Kim، نويسنده , , Young-Hee and Kim، نويسنده , , Daejeong and Kim، نويسنده , , Dong Myeong and Cho، نويسنده , , Seong-Ik and Ahn، نويسنده , , Jin-Hong and Chung، نويسنده , , Jin-Yong، نويسنده ,
Abstract :
A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80% larger than the conventional pump with the sacrificial 10% area penalty. This new pump is regarded to be suitable to sub-1-V-VCC DRAMs with the negative-word-line (NWL) scheme, where the dynamic current consumption is expected to be very large.
Keywords :
Large-current-output charge pump , Low-voltage charge pump , Low-voltage circuit , Low-voltage generator , Negative word line , Low-voltage DRAM circuit , Low-voltage memory circuit
