Design of fourth-order ΔΣ modulator for the D/A conversion of audio signals

This paper describes an efficient circuit technique to minimize the hardware consumption for a digital fourth-order single loop ΔΣ modulator. The modulator employs a simple bit-shifting and the ROM selection scheme for multiplications and the new buffer-and-routing ROM structure. Fabricated in a standard digital 0.35 μm CMOS technology, the modulator achieves a signal-to-noise ratio (SNR) of 96 dB with an oversampling ratio of 256 under the supply of 2.0 V.