Title of article
A fully integrated fractional-N frequency synthesizer with a wideband VCO and a 3-bit 4th order Σ–Δ modulator for GSM/GPRS/EDGE applications
Author/Authors
Lee، نويسنده , , Han-il and Ahn، نويسنده , , Tae-won and Cho، نويسنده , , Je-Kwang and Lee، نويسنده , , Kun-seok and Nah، نويسنده , , Kyung-Suc and Park، نويسنده , , Byeong Ha and Han، نويسنده ,
Issue Information
دوماهنامه با شماره پیاپی سال 2005
Pages
6
From page
259
To page
264
Abstract
A fully integrated fractional-N frequency synthesizer (FNFS) in 0.5 μm SiGe BiCMOS technology is implemented. To cover wideband frequency operation, a switched capacitor bank LC tank VCO and an Adaptive Frequency Calibration (AFC) technique are used. A 3-bit 4th order Σ–Δ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz, and agile switching time. The experimental results show −80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and −129 dBc/Hz out-of-band phase noise at 400 kHz-offset frequency. The fractional spurs are less than −70 dBc/Hz at 300 kHz offset frequency and the reference spur is −75 dBc/Hz. The lock time is less than 150 μs. The proposed synthesizer consumes 19.5 mA from a single 2.8 V supply voltage and meets the requirements of GSM/GPRS/EDGE applications.
Keywords
Frequency synthesizer , PLL , VCO , transceiver , WCDMA/GPRS/GSM
Journal title
Current Applied Physics
Serial Year
2005
Journal title
Current Applied Physics
Record number
1769812
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