Symmetric tunnel field-effect transistor (S-TFET)

A novel heterojunction symmetric tunnel field-effect transistor (S-TFET) has been proposed and investigated, for the first time, in order to address the inborn technical challenges of the conventional p-i-n TFET (i.e., asymmetric TFET). With a band-to-band tunneling process between the germanium source/drain region and the silicon channel region, the theoretical limit of the subthreshold slope (SS) can be overcome (i.e., SS ∼ 45 mV/decade). The bidirectional current flow in the S-TFET is implemented with a p-n-p structure. And better performance in the S-TFET is achieved with a thin silicon-pad layer below the source/drain regions. The effects of source/drain/channel doping concentration and thickness on the performance of the device are investigated in order to create an S-TFET design guideline. In the future, the S-TFET will be one of the promising device structures for ultra-low-power applications, especially in integrated circuits that operate with a half-volt power supply voltage.