Scalable DC Model of High Voltage SOI-LDMOS

This paper presents a scalable dc model for high voltage silicon on insulator lateral double diffused MOS (SOI-LDMOS) transistor scaled for different geometries as well as temperatures, assuming uniform doping for the channel. The device is analyzed and curves for velocity and voltages are plotted, for each of the device regions. Based on this analysis, the model is developed. Here MM20 model is used for the channel and drift region under the thin gate oxide. New model developed for the drift region under the field oxide, which exhibits quasi-saturation, is scaled for different lengths of the channel region, the drift region under the thin gate oxide and drift region under thick gate oxide, by taking into consideration the results of analysis. Also taken into account is the drift length modulation, at high gate and drain voltages. Temperature dependent modeling of the device is also done. The model developed exhibits high level of accuracy with the device simulated using MEDICI, over wide range of temperatures and different lengths of each of the regions