Design a Novel Based Fir Filter Architecture for High Speed

Finite Impulse Response (FIR) filter which deals with the new algorithm of Reconfigurability and low complexity. The algorithm that synthesizes multiplier block with low hardware requirement suitable for implementation as part of full-parallel FIR filter. Minimizing multiplier block logic depth and pipeline registers is shown to have the greatest influence in reducing FPGA area cost. In addition to providing lower area solutions than existing algorithms, comparisons with equivalent filters generated using the distributed arithmetic technique demonstrate further area advantages of the new algorithm. In the proposed architectures pipeline is introduced so that speed is increased by decreasing the delay. This technique used in the processor in which the data processing part is divided into many stages separated by register. Thus every storage can process one instruction in a clock cycle and the instruction move forward in the pipeline. Thus the processor can execute many instructions in much lesser time