Efficient Design of Half Adder and Half Subtractor Using New SN Reversible Gate

In the recent years, the reversible logic design attracting more interest due to its low power consumption. Reversible logic is very important in low power circuit design. Reversible logic has extensive applications in quantum computing, low power VLSI design, nano technology and optical computing. The classical set of gates such as AND, OR and EXOR are not reversible. This paper proposes a new 3 * 3 reversible gate called “SN “reversible gate. The proposed gate is used to design efficient adder and subtractor units. The proposed gate can be used to implement AND, XOR, XNOR and NOT gates. It is demonstrated that the adder/subtractor architectures designed using the proposed gate are much better and optimized, in terms of reversible gates and garbage outputs. Thus this paper provides the initial threshold to building of more complex system which can be execute more complicated operations using reversible logic