Low Power Designing of PLL with 0.125µm CMOS Technology

This paper deals with the designing of Low Power PLL by reducing power consumtion of VCO to generate well-timed on chip clock signals for digital signals. Switching of digital system introduce power supply or substrate noise which perturb the more sensitive blocks in VCO and clock buffer. Since power dissipation in PLL is small fraction of total active power but it increase with increasing operating frequency of digital system. This paper is describing the design of a fully-integrated low-jitter PLL for low power application. To achieve the low jitter performance, our work is proposed on jitter reduction method on both system and circuit level. The results are verified for both circuit and system level. The PLL is implemented in 0.25 ?m CMOS technology and consumes 10mW from a 2.5V supply