FPGA Based Iterative Processor for P to R and R to P Conversion

The high processing speed required by DSP applications is not very common. High performance general purpose microprocessors can provide computing speed only in conjunction with arithmetic co-processors. The DSP functions, transforms implementation requires implementation of various transcendental functions. Such as SINE,COS etc. These functions could be implemented in hardware using the traditional multiplier and accumulator based approach which causes the system to be slower. The CORDIC algorithm is an efficient method for implementation of these functions. The CORDIC algorithms uses only shift and add technique to perform the vector rotation in two dimensional vector space. Thus it avoids the use of traditional multiplier and accumulator unit [MAC unit] which generally is the bottleneck for the faster systems. In addition there are several algorithms such as CORDIC, NTT or Error Correction algorithms, where FPL technology has been proven to be more efficient than a PDSP. This paper attempts to explorer FPGA implementation of CORDIC algorithm for computing elementary trignometric functions, square root used in most of the signal processing.