A new design of a low noise, low power consumption CMOS charge amplifier

In this paper, a new design of a low noise, low power consumption charge amplifier is described. Theoretical results show that an ENC (Input-referred Equivalent Noise Charge) reduction of 258 electrons for a detector capacitor CD of 10 pF has been obtained with regard to a conventional charge amplifier. A complete readout system including the proposed charge amplifier followed by a shaper amplifier has been realized in a 1.2 μm CMOS N-well process. The noise performance of 112 electrons at 0 pF with a slope of 34 electrons/pF for a shaping time of 200 ns and 1 mW power consumption has been obtained.