Gated Clock Implementation of Arithmetic Logic Unit (ALU)

Low power design has emerged as one of the challenging area in today’s ASIC (Application specific integrated circuit) design. With continuous decrease in transistor size, power density is increasing and there is an urgent need for reduction in total power consumption. Clock gating is one most effective technique for low power synchronous circuit design. Clock gating technique in low power design is used to reduce the dynamic power consumption. Clock signal in a synchronous circuit is used for synchronization only and hence does not carry any important information. Since clock is applied to each block of a synchronous circuit, and clock switches for every cycle, clock power is the major part of dynamic power consumption in synchronous circuits. Clock gating is a well known technique to reduce clock power. In clock gating clock to an idle block is disabled. Thus significant amount of power consumption is reduced by employing clock gating. In this paper an ALU design is proposed employing Gated clock for its operation. Design simulation has been performed on Xilinx ISE design suite, and power calculation is done by Xilinx Xpower analyzer. Results show that approximately 17% of total clock power consumption is reduced by gated clock implementation.