Title of article
Design and Simulation of Pipelined FFT Processor Using FPGA.
Author/Authors
Reddy، N. Amarnath نويسنده GMR institute of Technology, Rajam, INDIA , , Rao، D. Srinivasa نويسنده GMR institute of Technology, Rajam ,
Issue Information
روزنامه با شماره پیاپی سال 2013
Pages
5
From page
1361
To page
1365
Abstract
A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM). Unlike being stored in the traditional ROM, the twiddle factors in our pipelined FFT processor can be accessed directly. A novel simple address mapping scheme and the modified radix 4 FFT also proposed. Finally, the pipelined 64-point FFT processor can be completely implemented within 20.093ns.
Journal title
International Journal of Electronics Communication and Computer Engineering
Serial Year
2013
Journal title
International Journal of Electronics Communication and Computer Engineering
Record number
2002309
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