An Efficient Adiabatic CMOS Circuit Design Approach for Low Power Applications

One of the key issues in CMOS circuit design is the large amount of power being dissipated in the circuits. Energy recovering circuitry based on adiabatic principles is a relatively new technique used to implement low power dissipating circuits. By recycling the charge at capacitive nodes in the circuit, adiabatic logic families can achieve very low power dissipation. In this paper we had design and simulate the Inverter, Two-Input Nand gate, Two-Input Nor gate, Two-Input Xor gate, 2:1 Multiplexer on the basis of CMOS Logic and Adiabatic Switching logic using 180nm CMOS technology in Cadence design environment. Two adiabatic families are used in this work, Oneis the Positive Feedback Adiabatic Logic (PFAL) and the other is the Ef?cient Charge Recovery Logic (ECRL) Finally, the analysis of the average dynamic power dissipation with respect to the frequency and the load capacitance was done to show the amount of power dissipated by the CMOS, PFAL and ECRL family. The results shows that power saving of adiabatic circuit can reach more than 90% as compare to conventional static CMOS logic.