Reconfigurable Area {&} Speed Efficient Decimator Using DA Algorithm

Decimator is an important sampling device used for multi-rate signal processing in wireless communication systems. In this paper, a reconfigurable area & speed efficient multipliers less decimator is presented. DA has been use d to implement the proposed structure taking advantage of embedded LUT based structure of FPGAs. Efficient solution is designed using half band polyphase decomposition FIR structure. The proposed decimator has been designed with MATLAB Simulink and developed verilog code. Simulation is performed using ModelSim and functional verification is carried out using Xilinx synthesis tool (XST)10.1 and implemented on Spartan-3E based 3s500efg320-5 FPGA device. Improvement of 40% in speed and 50% in area has been observed as compared to MAC based approach.