A High Speed FIR Filter Architecture Based on Higher Radix Algorithm

Digital Signal Processing (DSP) is a field of utmost importance as it performs the processing of a digital signal. DSP techniques improve signal quality or extract important information by removing unwanted parts of the signal which is possible with the help of filters. A Finite Impulse Response (FIR) filters play a crucial role in many of the signal processing applications. The output is computed using Multiply And Accumulate (MAC) operations. In a conventional multiplication, the number of partial product rows is same as the number of bits in multiplier. Since the amount of hardware and the delay depends on the number of partial products to be added. The number of partial products can be reduced by using radix algorithm. A FIR filter based on radix-256 booth encoding is implemented which reduces the number of partial product rows in any multiplication by 8 fold. The obtained partial product rows are added using carry free RB addition. Then the RB output is converted back to Natural Binary (NB) form using RB to NB converter. The performance of radix-256 multiplier architecture for FIR filter is compared with computation sharing multiplier (CSHM). The radix-256 multiplication method for FIR filter is found to be faster in comparison to CSHM implementation.